As semiconductor memory devices, in particular DRAMs, increase in storage capacity and become more highly integrated, the need to quickly and effectively test the devices has become an increasingly important consideration in their design and manufacture.
The storage capacity of semiconductor memory devices, and in particular DRAMs, has on the average tended to quadruple every three to four years. While the memory capacity of DRAMs has steadily increased, the actual area on a semiconductor wafer occupied by a DRAM has remained relatively stable. Consequently, the elements which make up the DRAM have undergone substantial reductions in size over the years.
With these developments, several problems have arisen. The reduced size of the elements making up the DRAM has created an increased likelihood of defects in the end product. Also, the increased capacity of the DRAMs has substantially increased the time required to test the DRAMs for defects by conventional methods. It is known that the time required to perform such testing, depending upon the test patterns applied, increases at least by a factor of 2.sup.N with an increase in storage size of a factor N.
The testing done quite often requires the loading of identical information into large numbers of the memory cells. For example, burn-in, a standard test conducted on memory devices at the time of manufacture, requires writing all highs or all lows to all of the memory cells at some time during the testing process. Burn-in tests consist of: a.) elevating the voltage in the memory cells of the DRAM to a potential of at least one or two volts above the normal voltage the DRAM would experience during normal operation; b.) placing the DRAM in an ambient temperature higher than it would normally experience; and c.) maintaining these conditions for a specified period of time. Burn-in is designed to stress test various oxide or dielectric connections found throughout the DRAM. Since the size of the various elements and layers on the DRAM, including the oxide layers, has decreased with each increase in memory capacity, the assuring of quality oxide and dielectric layers has become increasingly important.
Given the fact that normal DRAM operation allows access to relatively few memory cells at any one time conventional tests which use the normal data paths to conduct the tests can only test a few memory cells at any one time. When semiconductor memory devices had capacities of only 1 K, 4 K, 16 K, etc., the time needed to complete the tests did not create any serious problems. However, nowadays, with memory devices having capacities of 4 MB, 16 MB, etc., conventional methods of testing are costly and time consuming.
Various methods to simultaneously write to multiple memory cells, known as flash writing, have been developed over the years. Some of the solutions to the DRAM testing problem have involved the fabrication of additional data paths to the bit lines of the memory array to provide an alternate path into the memory cells for flash writing. United Kingdom Patent GB2,232,744 provides an example of this approach. However, given the large number of bit lines in the memory array, the extra circuitry required adds additional unwanted complexity to the design and consumes an inordinate amount of space on the DRAM. Another alternative proposed involves adding additional circuitry to the column decoder of the memory array. Such additional circuitry would augment the capabilities of the column decoder so that the normal data paths could provide the channel for simultaneously writing to multiple memory cells. U.S. Pat. No. 4,991,139 provides an example of this approach. However, use of the augmented column decoder and normal data paths has the same disadvantages as using separate data paths to the bit lines. The circuitry required adds substantial complexity to the DRAM and requires substantial amounts of additional scarce space on the chip.
The challenge, thus, remains of providing a method for flash writing a DRAM for test purposes in a way that adds a minimal amount of extra circuitry and complexity to the structure of the DRAM.